The present invention relates to a semiconductor device that functions as a DTMOS or a MISFET having a heterojunction active region.
In recent years, portable information terminal units driven by a battery are widely used. In such units, there is a strong demand for reducing the power supply voltage without compromising high speed operations in order to prolong the battery lifetime. Reducing the threshold voltage is effective in realizing high speed operations. In this case, however, the leakage current at the time when the gate is off becomes large, so that it is inevitable that there should be a lower limit for threshold voltage.
As a device that can solve this problem and has a small leakage current at a low voltage and high driving ability, a device called DTMOS (Dynamic Threshold Voltage MOSFET) has been proposed, as disclosed in, for example, a literature “A Dynamic Threshold Voltage MOSFET (DTMOS) for Ultra-Low Voltage Operation”, by F. Assaderaghi et. al., IEDM94 Ext. Abst. P. 809.
FIGS. 1 and 2 are a cross-sectional view and a plan view schematically showing a conventional DTMOS structure, respectively. As shown in FIG. 1, the conventional DTMOS uses a SOI substrate including a p-type silicon substrate (p− Si Sub), a buried oxide film layer (Buried Oxide) and a semiconductor layer, which serves as a substrate active region. The conventional DTMOS further includes a gate insulator film (SiO2) on the substrate active region, a gate (n+ poly-Si), source and drain regions (n+ layer) in regions on both sides of the gate of the substrate active region, a channel region (a surface portion of the p layer) in a region between the source and drain regions of the substrate active region. A substrate region below and on the sides of the channel region (body) is connected to the gate electrode by wiring for electrical short-circuit. When a bias voltage Vg is applied to the gate while the gate is tied to the body, a forward bias voltage having the same magnitude as that of the gate bias voltage Vg is applied to the channel region via the body. Thus, this DTMOS has the same state as that of a regular MOS transistor at the time when the gate bias is off, and the body is biased in the forward direction as the gate bias voltage Vg is increased at the time when the gate bias is on (this occurs because the energy level of the conduction band edge of the channel region is decreased in the n-channel type MOS transistor shown in FIG. 1. Therefore, the threshold voltage Vt drops.
When such a DTMOS is compared with a regular MOS transistor (transistor where the gate and the body are not short-circuited) formed on a SOI substrate, the leakage current of the DTMOS is equal to that of the regular transistor at the time when the gate bias is off. On the other hand, since the threshold voltage drops at the time when the gate bias is on, as described above, the gate over drive effect increases, so that the driving ability increases significantly. Furthermore, in the DTMOS, there is substantially no electric potential difference between the gate and the channel region, and therefore the electric field in the vertical direction on the surface of the substrate is significantly small, compared with that of the regular transistor. As a result, the degradation of the mobility of carriers due to an increase of the electric filed in the vertical direction is suppressed, so that the driving ability is increased significantly.
Thus, the DTMOS functions as a transistor that can operate at high speed at a low threshold voltage, i.e., a low power supply voltage, as long as the operating voltage is in the range within which a parasitic bipolar transistor in the lateral direction generated between the n-type gate, the p-type body (base), and the n-type source (emitter) and drain regions (collector) is not on, and therefore the body current is not so large as to cause a practical problem.
However, in the case of such a DTMOS structure, in order to suppress standby current, it is necessary to limit the voltage to be applied to the gate to up to about 0.6V, at which a parasitic bipolar transistor in the lateral direction is on. This is because the base current (the gate current or the body current that flows between the gate and the body in the DTMOS) of the parasitic bipolar transistor in the lateral direction is determined substantially by the built-in potential of the silicon, and therefore the gate current or the body current (base current) becomes significantly large when the gate bias voltage Vg (base voltage) is about 0.6V.
FIG. 7 is a graph showing simulation results of the gate bias voltage dependence of the drain current and the body current. The bold broken line in FIG. 7 shows the drain current Id of the conventional DTMOS, and the thin broken line in FIG. 7 shows the body current Ib of the conventional DTMOS. In FIG. 7, simulation is conducted with respect to the DTMOS that operates as a p-channel type MOS transistor, and therefore the gate bias voltage is negative values. However, in the case of an n-channel type DTMOS, the gate bias voltage is positive. These simulation results were obtained, assuming that the impurity concentration of the body is 1×1018 atoms·cm−3, the gate length is 0.5 μm, and the thickness Tox of the gate insulator film is 10 nm. As seen from the curves of the broken lines in FIG. 7, in the conventional DTMOS shown in FIG. 1, the body current Ib is equal to or larger than the value (about 10−9 A) that causes a practical problem at 0.6V or more of the gate bias voltage. Therefore, in order to avoid this problem, the operating voltage range is limited to very narrow.
Furthermore, in the conventional DTMOS, the necessity of reducing the threshold voltage does not allow the impurity concentration of the body to be high. In fact, the above-described literature states that the concentration of the p-type impurity of the body is about 1.5 to 3×1017 cm−3. As a result, the resistance of the body becomes significantly high, so that the voltage drop at the body prevents efficient conduction of the electric potential of the gate to the channel region. As a result, a CR delay becomes detrimental to dynamic operations and inhibits high speed operations.
Moreover, since the concentration of the impurity of the body is low, the short channel effect that occurs when the gate length is made short becomes significant. This is because, when the gate length is short, the punch-through occurs readily between the source and the drain regions because of expansion of the depletion layer in the body. In other words, in the conventional DTMOS, it was practically difficult to improve the device performance or the integration degree by miniaturization of the size (miniaturization of the gate length) of the transistor.